A well known type of non-volatile cell is a nitride, read only memory (NROM) cell, described in such patents as Applicant's U.S. Pat. No. 6,490,204, entitled “Programming And Erasing Methods For An NROM Array”, and Applicant's U.S. Pat. No. 6,396,741, entitled “Programming Of Nonvolatile Memory Cells”, the disclosures of which are incorporated herein by reference.
Unlike a floating gate cell, the NROM cell has two separated and separately chargeable areas. Each chargeable area defines one bit. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) sandwich underneath a gate. When programming a bit, channel hot electrons are injected into the nitride layer. Programming an NROM cell may typically involve applying positive voltages to gate and drain terminals of the transistor, while the source may be floated.
Erasing an NROM cell requires decreasing the threshold voltage of the cell. Erasing an NROM cell, which is done in the same source/drain direction as programming, typically involves applying a negative voltage to the gate and a positive voltage to the drain, while the source may be floated. The negative gate voltage creates holes in the junction near the drain, typically through band-to-band tunneling. The holes may be accelerated by the lateral field near the drain and the ONO layer. As the holes accelerate towards the drain, they eventually achieve sufficient energy to be injected into the nitride layer, this being known as tunnel-assisted hot hole injection.
A concern with NROM cells, as well as for other kinds of non-volatile memory (NVM) cells, is drift or unintended changes in the threshold voltages of memory cells. For example, over time at room temperature, bits that are supposed to be in an erased state may experience an increase in threshold voltage.
There are several problems associated with the drift problem. The changes alter the state of the memory cell and the data value stored therein, thereby creating a data error. Such data errors are intolerable in many memory applications. The drift causes a loss in the margin of voltage level between the erased state voltage level and the read reference level. Accordingly, in the prior art, the erase verify level may be set at a certain low voltage level, taking into account a factor of safety so as to distance the erased state voltage level from the read reference level. This is referred to as maintaining a “window” between the erased state voltage level and the read reference level. There may be likewise a “window” between the programmed state voltage level and the read reference level. One way of combating the margin loss would be to maintain a large window that would separate the erased state voltage level from the read reference level even after drift in the erased state voltage level over time. However, this in turn causes other problems. A larger window may lower reliability by detrimentally affecting cycling and retention. In addition, the larger window necessitates longer write times, thereby causing a loss in performance.
Applicant's U.S. patent application Ser. No. 09/983,510, entitled “Method For Erasing A Memory Cell”, corresponding to published PCT patent application WO 03/036650 (PCT/IL02/00855), provides further methods for erasing a bit of a memory cell so as to reduce the drift of the threshold voltage thereafter. After applying an erase pulse to a bit, the bit is read to check if the bit has passed an erase verify level. If the bit has passed the erase verify level, then at least one more erase pulse is applied to that bit. The extra erase pulse may be applied with the same or different voltage levels of gate and drain and for the same or different time duration as the previous erase pulse.
The application of one or more extra erase pulses lowers the initial threshold voltage of the erased bit. This provides several advantages. First, it will take longer for the threshold voltage to drift upwards than the prior art. Second, the erase verify level may be set at a higher voltage level than the prior art. Third, the application of the extra erase pulse or pulses may actually decrease the slope of the increase in threshold voltage level of the erased bit.
However, the extra erase pulse may have the disadvantage of increasing the number of holes in the ONO stack dielectric, which may increase the retention loss.